1. Field of the Invention:
The present invention relates to a semiconductor memory and a method of fabricating the same, and more particularly to a semiconductor memory having a one-transistor/one-capacitor structure for storing information as a charge in a data storage area (capacitor), and to a method of fabricating such a semiconductor memory.
2. Description of the Prior Art:
Generally, in a semiconductor memory, it is required to decrease the memory cell area with increasing the integration. However, the area of the capacitor portion in the memory cell cannot be made so small, because it is necessary for the capacitor portion to have a certain capacitance. Accordingly, some structures in which the capacitor portion is formed over a transistor have been proposed. For example, a stacked memory cell structure in which the capacitor is formed below the bit line, and a stacked memory cell structure in which the capacitor is formed above the bit line as shown in FIG. 9 have been proposed (S. Kimura, A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-line Structure, IEDM Tech. Dig., pp. 596-599, Dec. 1988).
In FIG. 9, isolation regions 52 are formed in a semiconductor substrate 51. Transistors 53a and 53b are formed at the surface of the semiconductor substrate 51. A bit line 54 is formed on the semiconductor substrate 51. A first interlayer insulating film 55 is formed on the entire surface of the semiconductor substrate 51. A contact hole 56 is formed and a node electrode 57 is formed in the contact hole 56 and above the transistor 53a. A capacitance insulating film 58 is formed over the entire surface of the semiconductor substrate 51. A contact hole 58a is formed and a first level interconnection layer 59a is formed. A second interlayer insulating film 510 is formed on the entire top face. A contact hole 511 is formed through the second interlayer insulating film 510, and a second level interconnection layer 512 is formed in the contact hole 511 and on the second interlayer insulating film 510. As shown, the first level interconnection layer 59a is disposed above the capacitor constituted by the node electrode 57, the capacitance insulating film 58, and a plate electrode 59.
As shown in FIG. 9, usually in the prior art structure, the plate electrode 59 and the first level interconnection layer 59a are formed as separate layers. The plate electrode 59 is formed from a single layer of phosphorus-doped polysilicon or the like. The first level interconnection layer 59a is formed in a single layer structure of Al-Si-Cu, etc. or formed in a two-layered structure with an additional layer of a barrier metal such as TiN/Ti, as the underlying layer.
However, in the above prior art structure, since the node electrode 57 and plate electrode 59 of the capacitor are formed only in the memory cell area, the step in level between the memory cell area and the peripheral circuit area becomes larger. Thus, in a later step for forming the first level interconnection layer by photolithography, the focuses are different between the memory cell area and the peripheral circuit area, which causes a problem in terms of patterning accuracy. Furthermore, the increased step at the contact hole 58a in the peripheral circuit area poses a problem as it may lead to the discontinuity of the first level interconnection layer 59a in the contact portion.
On the other hand, with the miniaturization of interconnection patterns, it has been proposed that an interconnection structure consisting of two or more layers, such as a conductive layer of Al-Si-Cu, etc. and a barrier metal of TiN/Ti, etc., should provide better reliability of interconnections in terms of stressmigration and electromigration, as compared with the conventional single layer structure of Al-Si-Cu, etc. (T. Kikkawa, A quarter-micron interconnection technology using Al-Si-Cu/TiN alternated layers, IEDM Tech. Dig., pp. 281-284, Dec. 1991)